Section: Dissemination

Teaching - Supervision - Juries

• C. Wolinski is the Director of Esir .

• O. Sentieys is responsible of the ”Embedded Systems” major of the SISEA Master by Research.

• D. Chillet is the responsible of the ICT Master of University of Science and Technology of Hanoi.

• C. Killian is the responsible of the second year of the Physical Measurement DUT at IUT, Lannion.

Enssat stands for ”École Nationale Supérieure des Sciences Appliquées et de Technologie” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Lannion. istic is the Electrical Engineering and Computer Science Department of the University of Rennes 1. Esir stands for ”École supérieure d'ingénieur de Rennes” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Rennes.

• E. Casseau: signal processing, 21h, Enssat (L3)

• E. Casseau: low power design, 6h, Enssat (M1)

• E. Casseau: real time design methodology, 57h, Enssat (M1)

• E. Casseau: computer architecture, 24h, Enssat (M1)

• E. Casseau: VHDL design, 42h, Enssat (M1)

• E. Casseau: SoC and high-level synthesis, 33h, Master by Research (SISEA) and Enssat (M2)

• S. Derrien, optimizing and parallelising compilers, 14h, Master of Computer Science, istic (M2)

• S. Derrien, advanced processor architectures, 8h, Master of Computer Science, istic (M2)

• S. Derrien, high level synthesis, 20h, Master of Computer Science, istic (M2)

• S. Derrien, computer science research projects, 10h, Master of Computer Science, istic (M1)

• S. Derrien: introduction to operating systems, 8h, istic (M1)

• S. Derrien, principles of digital design, 20h, Bachelor of EE/CS, istic (L2)

• S. Derrien, computer architecture, 48h, Bachelor of Computer Science, istic (L3)

• F. Charot: computer architectures, 16h, Esir (L3)

• D. Chillet: embedded processor architecture, 20h, Enssat (M1)

• D. Chillet: multimedia processor architectures, 24h, Enssat (M2)

• D. Chillet: low-power digital CMOS circuits, 6h, Telecom Bretagne (M2)

• C. Killian: digital electronics, 62h, iut Lannion (L1)

• C. Killian: signal processing, 36h, iut Lannion (L2)

• C. Killian: automated measurements, 56h, iut Lannion (L2)

• C. Killian: measurement chain, 58h, iut Lannion (L2)

• C. Killian: embedded systems programming, 12h, iut Lannion (L2)

• C. Killian: automatic control, 18h, iut Lannion (L2)

• A. Kritikakou: computer architecture 1, 32h, istic (L3)

• A. Kritikakou: computer architecture 2, 44h, istic (L3)

• A. Kritikakou: C and unix programming languages, 102h, istic (L3)

• A. Kritikakou: operating systems, 96h, istic (L3)

• A. Kritikakou: multitasking operating systems, 20h, istic (M1)

• O. Sentieys: VLSI integrated circuit design, 24h, Enssat (M1)

• O. Sentieys: VHDL and logic synthesis, 18h, Enssat (M1)

• C. Wolinski: computer architectures, 92h, Esir (L3)

• C. Wolinski: design of embedded systems, 48h, Esir (M1)

• C. Wolinski: signal, image, architecture, 26h, Esir (M1)

• C. Wolinski: programmable architectures, 10h, Esir (M1)

• C. Wolinski: component and system synthesis, 10h, Master by Research (istic ) (M2)

• PhD: Gabriel Gallin, Hardware arithmetic units and cryptoprocessors for hyperelliptic curve cryptography, Nov. 2018, A. Tisserand.

• PhD: Aymen Gammoudi, Scheduling and Mapping Strategies for Software Tasks on Energy-Constrained Reconfigurable Architectures, June 2018, D. Chillet, M.Khalgui.

• PhD: Jiating Luo, Architectural and Protocol Exploration for 3D Optical Network-on-Chip, Jul. 2018, D. Chillet, C. Killian, S. Le-Beux.

• PhD: Mai-Thanh Tran, Towards Hardware Synthesis of a Flexible Radio from a High-Level Language, Nov. 2018, E. Casseau, M. Gautier.

• PhD: Van Dung Pham, Architectural Exploration of Network Interface for Energy Efficient 3D Optical Network-on-Chip, Dec. 2018, O. Sentieys, D. Chillet, C. Killian, S. Le-Beux.

• PhD: Rafail Psiakis, Performance Optimization Mechanisms for Fault-Resilient VLIW Processors, Dec. 2018, A. Kritikakou, O. Sentieys.

• PhD: Simon Rokicki, Hardware acceleration of Dynamic Binary Translation, Dec. 2018, S. Derrien, E. Rohou.

• PhD in progress: Minh Thanh Cong, Hardware Accelerated Simulation of Heterogeneous Multicore Platforms, May 2017, F. Charot, S. Derrien.

• PhD in progress: Minyu Cui, Energy-Quality-Time Fault Tolerant Task Mapping on Multicore Architectures, Oct. 2018, E. Casseau, A. Kritikakou.

• PhD in progress: Petr Dobias, Energy-Quality-Time Fault Tolerant Task Mapping on Multicore Architectures, Oct. 2017, E. Casseau.

• PhD in progress: Mael Gueguen, Improving the performance and energy efficiency of complex heterogeneous manycore architectures with on-chip data mining, Nov. 2016, O. Sentieys, A. Termier.

• PhD in progress: Van-Phu Ha, Application-Level Tuning of Accuracy, Nov. 2017, T. Yuki, O. Sentieys.

• PhD in progress: Jaechul Lee, Energy-Performance Trade-Off in Optical Network-on-Chip, Dec. 2018, D. Chillet, C. Killian.

• PhD in progress: Audrey Lucas, Software support resistant to passive and active attacks for asymmetric cryptography on (very) small computation cores, Jan. 2016, A. Tisserand.

• PhD in progress: Thibaut Marty, Compiler support for speculative custom hardware accelerators, Sep. 2017, T. Yuki, O. Sentieys.

• PhD in progress: Romain Mercier, Fault Tolerant Network on Chip for Deep Learning Algorithms, Oct. 2018, D. Chillet, C. Killian, A. Kritikakou.

• PhD in progress: Genevieve Ndour, Approximate Computing with High Energy Efficiency for Internet of Things Applications, Apr. 2016, A. Tisserand, A. Molnos (CEA LETI).

• PhD in progress: Joel Ortiz Sosa, Study and design of a digital baseband transceiver for wireless network-on-chip architectures, Nov. 2016, O. Sentieys, C. Roland (Lab-STICC).

• PhD in progress: Davide Pala, Non-Volatile Processors for Intermittently-Powered Computing Systems, Jan. 2018, O. Sentieys, I. Miro-Panades (CEA LETI).

• PhD in progress: Joseph Paturel, Design-space exploration of fault-tolerant multicores, Sep. 2018, O. Sentieys, A. Kritikakou.

• PhD in progress: Nicolas Roux, Sensor-aided Non-Intrusive Appliance Load Monitoring: Detecting Activity of Devices through Low-Cost Wireless Sensors, Oct. 2016, O. Sentieys, B. Vrigneau.